Why Chiplet Power Delivery Networks Break Traditional PDN Rules

Power delivery networks (PDNs) in chiplet systems don't follow the playbook that worked for monolithic chips. The distributed nature of chiplet designs creates unique challenges that traditional PDN strategies simply can't handle.

Photo by David Brown on Pexels.

Consider voltage domain isolation. In a monolithic design, you might have three or four distinct voltage domains spread across different functional blocks. With chiplets, each die can have its own optimized process node and power requirements. A 5nm compute chiplet running at 0.75V sits next to a 12nm I/O die operating at 1.8V, connected through an interposer that needs yet another voltage rail.

graph TD
    A[Compute Chiplet 0.75V] --> D{Interposer Bridge}
    B[Memory Chiplet 1.1V] --> D
    C[I/O Die 1.8V] --> D
    D --> E[Package Substrate]
    F[VRM 1] --> A
    G[VRM 2] --> B
    H[VRM 3] --> C
    I[Interposer Rail] --> D

This creates a decoupling capacitor nightmare. Traditional monolithic designs place decaps based on current density maps and switching frequency analysis. Chiplet systems break this model because current paths now cross die boundaries through micro-bumps or hybrid bonding interfaces.

The resistance and inductance of these inter-chiplet connections become the dominant factors in PDN impedance, not the on-die power grid. A compute chiplet might see perfectly clean power locally, but voltage droop spikes whenever it needs to communicate with the memory chiplet.

Heterogeneous integration makes this worse. Different process nodes have different power delivery requirements, but they're now sharing the same package substrate. The 5nm logic chiplet needs ultra-low voltage ripple for its razor-thin noise margins. Meanwhile, the 28nm analog chiplet can tolerate much higher ripple but draws massive current spikes during transmission events.

Package designers solve this with distributed VRM approaches that would seem excessive in monolithic designs. Instead of one central voltage regulator module feeding the entire package, chiplet systems often deploy dedicated VRMs for each die, plus intermediate regulation on the interposer itself.

TSMC's CoWoS-S implementations demonstrate this philosophy. Each HBM stack gets its own power delivery path, isolated from the processor chiplets. The silicon interposer carries not just signal routing but dedicated power planes for each voltage domain. This redundancy costs area and complexity, but it's the only way to maintain power integrity across heterogeneous dies.

Thermal coupling complicates the power story further. In monolithic designs, hotspots spread heat relatively evenly across the die. Chiplet packages create thermal gradients between dies that affect power consumption patterns. A hot compute chiplet increases leakage current in adjacent memory chiplets, creating power delivery demands that traditional PDN modeling doesn't predict.

Intel's Foveros technology addresses this through three-dimensional power delivery. Instead of routing all power through the base die, Foveros allows direct power delivery to upper chiplets through through-silicon vias (TSVs). This shortens current paths and reduces the PDN impedance that kills performance in stacked configurations.

The result? Chiplet PDN design requires simulation tools that model electromagnetic coupling between dies, something that monolithic PDN analysis never needed. Power integrity verification now includes cross-chiplet interaction effects, inter-die communication currents, and heterogeneous thermal profiles.

Modern chiplet packages often dedicate 40% or more of their interconnect resources to power delivery, compared to 20-25% in equivalent monolithic designs. This overhead is the tax you pay for the flexibility to mix process nodes and functional blocks.

Successful chiplet PDN design starts with partitioning power domains at the system level, not the die level. Each chiplet becomes a power island with carefully controlled interfaces to its neighbors. The days of treating power delivery as an afterthought in silicon planning are over — in chiplet systems, the PDN defines what's possible at the package level.