The Architecture of Next-Gen Silicon
Random die placement on advanced packages destroys yield in ways traditional models never predicted. Here's what the math actually looks like.
P. NakamuraDisaggregating SoCs into chiplets doesn't just split silicon, it splits trust. Here's why securing die-to-die interfaces is genuinely unsolved.
P. NakamuraKnown-good-die testing is the unglamorous bottleneck throttling chiplet yield and cost. Here's how the industry is solving it, and where it's still stuck.
P. NakamuraCo-packaged optics and silicon photonics are rewriting the rules for chiplet interconnect bandwidth, here's what that means for next-gen heterogeneous designs.
P. NakamuraWafer-to-wafer bonding offers unmatched interconnect density, but yield math punishes it harshly. Here's why that tradeoff is shifting.
P. NakamuraEmbedded bridge dies are turning passive silicon interposers into active routing layers, here's what that means for chiplet bandwidth and cost.
P. NakamuraDie-to-die latency isn't just a spec footnote, it's quietly determining which functions can be disaggregated into chiplets and which cannot.
P. NakamuraThermal resistance is the hidden tax on chiplet density. Here's how packaging engineers are fighting back with new materials and die-stacking strategies.
P. NakamuraHow chiplet designs force radical changes in power delivery networks, from voltage domains to decap placement strategies.
P. NakamuraWhy silicon interposers deliver superior signal integrity and density for AI chiplet interconnects compared to organic substrates.
P. NakamuraDistributed memory controllers in chiplet designs solve bandwidth bottlenecks that monolithic processors can't touch.
P. NakamuraIntel's EMIB horizontal integration outperforms vertical fan-out packaging for AI chips despite industry hype around 3D stacking.
P. NakamuraSamsung's I-Cube4 and TSMC's SoIC represent two distinct approaches to vertical chiplet stacking and 3D integration.
P. NakamuraAMD's MI300X uses advanced 2.5D packaging to outmaneuver Nvidia's H100 in AI workloads through superior chiplet integration.
P. NakamuraThe Universal Chiplet Interconnect Express standard could do for chiplets what PCIe did for expansion cards. Here is what matters.
P. NakamuraTSMC and Intel are taking different packaging approaches to the same chiplet future. Both strategies have real tradeoffs.
P. Nakamura