How Chiplet Partition Boundaries Drive PCIe Lane Allocation Before Any RTL Is Synthesized

Most engineers think PCIe lane allocation is a logic problem. Assign lanes in the RTL, close timing, hand off to the package team. That sequence feels natural because it mirrors how monolithic SoC design has worked for two decades.

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With chiplet-based designs, that sequence is backwards.

By the time synthesis opens, the number of PCIe lanes available to each die is already constrained by decisions made weeks or months earlier: how the system was partitioned across dies, where the die-to-die (D2D) interface boundary was drawn, and how much substrate routing bandwidth was reserved for each chiplet. Change those decisions late, and you are not editing RTL. You are renegotiating the package stackup.

Here is why that happens, and what the decisions actually look like in practice.

Partition Boundaries Are Bandwidth Budgets

When you split a monolithic design into chiplets, every signal that crossed an internal bus becomes a die-to-die interconnect. PCIe controllers are among the worst offenders. A single x16 PCIe 5.0 interface demands 32 differential pairs in each direction, plus reference clocks, resets, and sideband signals. Route all of that across a D2D boundary and you have consumed a meaningful slice of the interconnect budget on that edge.

The D2D interface itself is not free. UCIe, for example, defines a standard module pitch. Each module delivers a fixed number of signal bumps to the substrate or interposer. If your partition boundary forces the PCIe controller to sit on a different die from the PCIe PHY, you have to route those 32+ differential pairs through that bump array. The available modules determine whether you can do that at all, and at what speed.

This is where partition decisions become lane-count decisions. Assign the PHY to the I/O chiplet and the controller to the compute die, and you need enough D2D bandwidth to carry full-rate PCIe traffic. Miss the bump budget, and you cut lane width. Cut lane width, and system architects downstream will spend months trying to recover bandwidth through software tricks that never fully work.

The Substrate Routing Problem Is Invisible Until It Isn't

Organic substrates have a finite number of routing layers and a minimum trace pitch. High-speed differential pairs require controlled impedance, guard traces, and via antipad discipline. None of that is free in terms of layer consumption.

A chiplet that exports PCIe lanes directly to a connector or off-package device needs those pairs routed from the die bumps through the substrate to the edge or to a retimer. If the substrate is already heavily loaded carrying HBM command/address buses, D2D UCIe channels, and power delivery copper, there may not be physical room for additional PCIe lanes without adding layers. Each added layer costs money and delivery time.

Package engineers who see the full routing load early can flag this. When they see it after RTL freeze, they have less room to maneuver.

graph TD
    A[System Partition Decision] --> B{PCIe Controller Placement}
    B --> C[Same Die as PHY]
    B --> D[Different Die from PHY]
    C --> E[Direct Substrate Routing]
    D --> F[D2D Bump Budget Consumed]
    F --> G{Sufficient UCIe Modules?}
    G --> H[Full Lane Width Preserved]
    G --> I[Lane Width Reduced]
    E --> H

What Good Co-Design Actually Looks Like

The teams doing this well run a substrate routing feasibility pass before partition boundaries are finalized. Package engineers get a spreadsheet of candidate partitions, each with a signal count per die edge, and they return a routing score: feasible, feasible with layer adder, or infeasible. That score feeds back into the partition decision before any RTL is written.

Some teams go further. They model D2D interconnect bandwidth at partition time using the target D2D PHY spec (UCIe, or a proprietary variant) and sanity-check it against the peak PCIe throughput the system needs to deliver. If the D2D link cannot carry that traffic without saturation, the partition moves. Cheap to do at week two of the project. Extremely expensive at week forty.

The other practice worth noting: keeping the PCIe PHY and controller on the same die whenever the power and area budget allows. Avoiding the D2D crossing entirely sidesteps the bump budget problem. It is not always possible, especially when process node choices differ between analog PHY and digital controller. But where it is possible, the substrate routing team will thank you.

The Broader Principle

Chiplet design rewards people who think about physical constraints before logical ones. PCIe lane allocation sits at exactly that intersection: a logical quantity (how many lanes does this device have?) that is actually determined by physical decisions made before synthesis. Partition boundaries, bump budgets, substrate layer counts, D2D PHY module pitch. These set the ceiling. RTL fills in the space below it.