How Chiplet Disaggregation Forces a Complete Rethink of Signal Integrity Budgets

Signal integrity was a manageable problem when everything lived on one die. You closed your timing, ran your SI simulations, handed the netlist to your package team, and called it done. Disaggregation broke that workflow in ways that aren't obvious until you're staring at a 28 Gbps die-to-die link that keeps failing at temperature.

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The root issue is boundary ownership. On a monolithic die, the signal path from transmitter to receiver is fully visible to a single team running a single set of tools. Chiplets create physical gaps, substrate routing, microbumps, bridges, RDL layers, that sit between the die-level simulation domain and the package-level simulation domain. Neither team owns the full channel. Both teams model their piece. The handoff between those models is where SI budgets quietly fall apart.

What the Budget Actually Contains

A traditional serial link SI budget accounts for insertion loss, return loss, crosstalk, jitter accumulation, and eye margin. When the channel is entirely on-package, you can treat the bump and trace as a lumped element or a short transmission line. Acceptable. When the die-to-die link spans two chiplets connected through a silicon bridge or RDL fanout, the channel topology looks like this:

graph TD
    A[TX Chiplet Bump Array] --> B(Microbump to Bridge)
    B --> C[Silicon Bridge Trace]
    C --> D(Microbump to Substrate)
    D --> E[Organic Substrate Trace]
    E --> F(Microbump to Bridge)
    F --> G[Silicon Bridge Trace]
    G --> H(RX Chiplet Bump Array)

Each transition, die to bump, bump to bridge, bridge to substrate, substrate back to bridge, introduces an impedance discontinuity. Stack six of those discontinuities in series and you're not looking at a transmission line anymore. You're looking at a resonant cavity with a Q factor that depends on bump pitch, dielectric properties, and trace geometry, all of which vary across vendors and process nodes.

The UCIe physical layer specification acknowledges this. At 32 Gbps per lane, the channel loss budget for a short-reach chiplet link caps insertion loss at roughly 6 dB. That sounds generous until you realize that microbump transitions alone can consume 1-2 dB each, and a two-chiplet link with bridge routing can have four of them. Margin evaporates fast.

Where Multi-Vendor Designs Get Punished

Homogeneous chiplet stacks, same foundry, same bump rules, validated through one package design kit, give you enough consistency to make SI closure tractable. Heterogeneous stacks, where chiplets come from different foundries with different bump pitches and pad stack rules, are a different problem entirely.

Consider a design pairing a logic chiplet from TSMC N3 with an analog front-end from a 28nm specialty node. The bump pitch mismatch alone (say, 25 µm vs. 55 µm) forces RDL fanout between them. That RDL adds trace length, changes the reference plane geometry, and introduces additional vias. Each of those changes shifts the channel's impedance profile. Your SI team now needs S-parameter models from both chiplet vendors, an accurate 3D EM model of the RDL transition, and a substrate model from the OSAT, all stitched together in a single channel simulation. Getting those models to agree on reference impedance conventions is a negotiation that can take weeks.

This isn't a tools problem, exactly. The tools exist: Ansys HFSS, Cadence Clarity, Keysight ADS can all handle multi-domain channel analysis. The problem is data availability and model fidelity at the early design stages when SI-driven decisions about bump pitch, link topology, and equalization depth actually need to be made.

Equalization Is Not a Free Lunch

When SI margins are tight, the reflex is to add equalization: CTLE on the receiver, FFE on the transmitter, maybe DFE if you need it. That works on PCIe or SerDes links where the channel is well-characterized and power budgets are loose. Chiplet links have tighter power constraints. A 64-tap DFE at 32 Gbps draws non-trivial power per lane, and die-to-die links commonly run hundreds of lanes in parallel. The aggregate power cost of compensating for a poorly modeled channel can easily exceed the power saved by disaggregating in the first place.

The smarter path is to treat SI as a physical design input, not a post-layout fix. Bump pitch, via placement, and RDL routing rules all need to be chosen with channel insertion loss in mind before any schematic is finalized. That requires package engineers and chiplet architects to share a common channel model database from the earliest planning phases, not after tape-out, when the geometry is locked.

Disaggregation gives you yield, reuse, and node flexibility. The price is that signal integrity becomes a system-level discipline instead of a per-team checkbox. Teams that treat it that way ship working silicon. Teams that don't find out the hard way that a microbump is not the same as a wire.