How Photonic Interconnects Are Closing the Last Gap in Chiplet-to-Chiplet Bandwidth

Electrical interconnects have carried the semiconductor industry a long way. But somewhere between 1.6 Tbps per optical port and the physics of copper traces at millimeter-scale pitch, the math stops working in your favor.

Photo by Nic Wood on Pexels.

That's where co-packaged optics, CPO, enters the conversation. Not as a curiosity, but as a near-term production decision that chiplet designers are actively weighing right now.

The Copper Wall Is Real

Every electrical die-to-die link fights the same enemies: resistance, capacitance, and skin effect. Push data rates past 112 Gbps per lane on copper, and signal integrity demands either expensive equalization circuits or shorter trace lengths, often both. Shorter traces mean tighter packaging constraints. Tighter packaging means more heat. More heat means the power budget for equalization grows again.

It's a loop with no clean exit.

Silicon photonics sidesteps most of it. Optical signals don't care about impedance matching the same way. Bandwidth-distance product for fiber is orders of magnitude higher than copper, and the modulation schemes available at optical frequencies, PAM-4, coherent QAM, extend reach without the SNR cliff that kills copper links above 224 Gbps.

What Co-Packaged Optics Actually Looks Like

The term gets thrown around loosely, so it's worth being specific. In a CPO implementation, optical engines, modulators, detectors, drivers, are integrated into the same package as the compute or switching die, rather than sitting in a pluggable transceiver module at the rack edge.

This matters enormously for latency and power. A pluggable QSFP-DD module might burn 14–20W per 400G port. Move the optical function inside the package and closer to the SerDes, and that number can drop toward 5W per 400G equivalent, a 2–3× reduction that compounds fast across a 512-port switch ASIC.

graph TD
    A[Compute/Switch Die] --> B(Optical Engine Die)
    B --> C[Fiber Array Unit]
    C --> D((Optical Fiber))
    B --> E[/Driver & TIA Circuitry/]
    A --> F{Package Substrate}
    F --> B

Intel, Ayar Labs, and Broadcom have each demonstrated variants of this topology, with differences primarily in where the laser source lives, on-package, off-package edge-coupled, or in an external light source unit. Each choice trades fabrication complexity against thermal isolation. There's no consensus winner yet; process maturity and yield economics will decide that.

The Chiplet Integration Question

Here's the part that specifically interests heterogeneous packaging engineers: a photonic chiplet is a chiplet like any other, and it demands the same integration decisions.

Do you bond it face-to-face with the compute die using hybrid bonding? Use an interposer to bridge electrical and photonic domains? Route electrical signals through EMIB-style bridges while keeping optical I/O on the package perimeter?

Each path has tradeoffs that aren't obvious until you're deep in the floorplan. Hybrid bonding maximizes bandwidth density between electrical and photonic dies but demands sub-micron alignment, hard when photonic dies carry delicate waveguide structures that don't tolerate the same bonding pressures as pure CMOS. Interposer-based approaches relax alignment requirements at the cost of added electrical hop length, which partially erodes the latency advantage you were chasing.

Fan-out wafer-level packaging is gaining traction here precisely because it lets the photonic and compute chiplets be placed with high precision on a redistribution layer without wafer-to-wafer bonding stress. TSMC's integrated fan-out (InFO) and equivalent processes from ASE are being actively evaluated for CPO applications, not because fan-out is new, but because its placement accuracy has improved enough to meet photonic alignment specs.

Why This Changes Chiplet Disaggregation Strategy

Once you accept that optical I/O is a first-class chiplet, disaggregation decisions shift. A memory controller chiplet optimized for HBM doesn't need photonic integration. A network interface chiplet almost certainly does. The question becomes how cleanly you can partition those functions at the package level, and whether your chosen interconnect standard (UCIe, BoW, or something proprietary) can carry the control plane between optical and compute domains without becoming a bottleneck itself.

Ayar Labs' TeraPHY approach embeds optical I/O directly into the compute package at densities approaching 20 Tbps per package. At that bandwidth envelope, the traditional model, compute package to external NIC to pluggable optics, looks structurally inefficient. Not marginally. Significantly.

The packaging community has spent a decade getting electrical chiplet interfaces right. Photonic integration reopens almost every assumption: floorplanning, thermal zoning, I/O placement, and even which process node makes sense for which function. That's not a complication. That's the interesting part.

The last bandwidth gap isn't closed yet. But the tools to close it are shipping samples, not whitepapers.