How 3D-IC Stacking Order Determines Power Delivery Before the First RTL Line Is Written

Most power delivery discussions in chiplet design focus on bump pitch, decap placement, and PDN impedance targets. Those matter. But there is an earlier decision that shapes every one of them: which die sits on top, which sits on the bottom, and what connects them in between. Stacking order in a 3D-IC is not a packaging afterthought. It is a first-order design variable that sets the ceiling on what PDN engineers can even attempt.

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Consider the geometry. In a face-to-face (F2F) bond, the top die's frontside metal connects directly to the bottom die's frontside metal through hybrid bonds or micro-bumps. Power can reach the upper die through the lower one, but every micron of path through the bottom die's routing layers adds resistance and inductance. Flip the stack to face-to-back (F2B), and now power enters the bottom die from the substrate, travels up through TSVs, and delivers to the top die's backside. TSV resistance is low, but TSV count is finite, and every TSV that carries power is a TSV not carrying signal.

This tradeoff is not abstract. TSMC's SoIC process, used in high-bandwidth memory arrangements and their own internal CPU stacking experiments, places compute dies above memory or base dies in F2B configurations precisely because the memory die has a well-characterized TSV grid that can double as a power delivery highway. The compute die sits on top and draws current from below through those TSVs. Clean. Predictable. But it also means the compute die's power budget is capped by the TSV density of whatever die it's bonded to.

Here is where stacking order becomes a pre-RTL constraint that most SoC architects don't confront early enough. If you spec a top die with 200W TDP and your base die TSV grid can only deliver 150W without violating IR-drop targets, you have a problem that no amount of PDN optimization will solve. You needed to flag it in the floorplan phase, before RTL was frozen.

graph TD
    A[Substrate / Package] --> B[Base Die: TSV Grid + Power Distribution]
    B --> C{Bond Interface: F2F or F2B?}
    C --> D[/F2B: Power via TSVs to Top Die Backside/]
    C --> E[/F2F: Power via Frontside Metal Routing/]
    D --> F((Top Die: Compute or Logic))
    E --> F

The thermal dimension compounds the electrical one. Heat wants to travel toward the heat sink, which sits above the stack in most configurations. Place a high-power compute die on top and you get short thermal resistance to the lid. Place it on the bottom and you are conducting heat through every stacked layer above it, each with its own thermal resistance contribution. Flip-chip bonded layers with underfill behave differently from hybrid-bonded layers with near-zero bond line thickness. The numbers diverge fast.

Intel's Foveros stacking puts an active base die underneath a top die, with the base die handling I/O, power management, and some cache functions. That distribution is deliberate. The base die runs cooler because it is doing less compute-intensive work; the top die runs hotter but sits closer to the heat spreader. Get this wrong and junction temperatures on the bottom die climb past safe operating limits with no thermal path relief available.

Power gating adds another layer of complexity. When a domain on the top die gates off, the current draw through the TSV grid drops sharply. That inductive kick propagates back into the base die's power rails. Decap placement on the base die must anticipate these transients, which means knowing the top die's power state machine before the base die's PDN is finalized. Two teams, two schedules, one shared problem.

What responsible early-stage chiplet co-design looks like in practice: power architects and packaging engineers need to agree on stacking order at the same meeting where die partitioning happens. Not a week later. Not after RTL is locked. The stacking order sets TSV budgets, which set power delivery headroom, which sets TDP limits per die, which gates what RTL can be synthesized at all.

There is real money here. A respun base die because the original TSV grid couldn't support the compute die's peak current draw can cost eight to twelve weeks and seven figures in mask costs. That is the price of treating stacking order as a packaging question rather than a system question.

The teams that get 3D-IC right are the ones who understand that vertical position in the stack is a specification, not a layout detail.