How Chiplet Pad-Limited Die Boundaries Force Package Substrate Routing Before Logic Partitioning Begins

Most engineers assume logic partitioning drives the rest of the chiplet design flow. Partition first, assign I/O second, hand the result to packaging. Clean. Linear. Wrong.

Photo by Nicola Narracci on Pexels.

The actual order in pad-limited designs runs the other way. When die I/O pad rings saturate before the silicon area does, the package substrate routing topology gets fixed at a point where RTL teams are still debating which functions belong on which die. That inversion has real consequences.

What Pad-Limited Actually Means

A die is area-limited when the active logic fills the silicon before the perimeter pad ring runs out of space. Pad-limited is the opposite condition: the I/O ring is full, but the interior still has room. At 7nm and below, logic density compounds faster than perimeter scales, so pad-limited conditions appear earlier in product planning than most teams expect.

Once you hit that ceiling, adding more signal bandwidth between chiplets requires either a larger die (expensive), a finer bump pitch (requires advanced packaging), or a rethink of which signals actually cross the die boundary. Each of those choices propagates directly into the substrate routing layer count, the interposer geometry, and ultimately the bill of materials.

The Routing Lock-In Problem

Package substrate routing is not infinitely flexible. Trace width, via stack geometry, and escape routing from the bump field all get committed when the substrate vendor receives the design rule kit and preliminary bump map. Vendors need those inputs months before tape-out. That schedule means the substrate design is running in parallel with, or even ahead of, detailed RTL partitioning.

Here's where pad-limited die boundaries tighten the knot. The bump map reflects pad placement. Pad placement reflects the I/O ring topology. The I/O ring topology reflects what the architect decided to expose at the die boundary. Change the partition later and the pad ring moves. Move the pad ring and the bump map changes. Change the bump map and the substrate escape routing unravels.

A single partition decision, made late, can invalidate weeks of substrate layout work.

graph TD
    A[Logic Partition Decision] --> B[I/O Ring Assignment]
    B --> C[Bump Map Generation]
    C --> D[Substrate Escape Routing]
    D --> E{Pad Ring Saturated?}
    E -->|Yes| F[Substrate Layer Count Increases]
    E -->|No| G[Routing Proceeds Normally]
    F --> H[Cost and Schedule Impact]

Why Teams Keep Getting This Wrong

Organizational separation is a large part of the answer. RTL architects own partition decisions. Package engineers own substrate design. These teams often run on different schedules, report to different managers, and use incompatible tooling. The handoff between them is a document, usually a spreadsheet, passed across an organizational gap.

That gap is exactly where pad-limited surprises land. The substrate team starts with a bump count derived from an early architectural estimate. The RTL team refines the partition and quietly increases the inter-die bandwidth requirement. Nobody updates the bump map in time. The substrate vendor has already committed layer count.

The result is either an emergency respin of the substrate, a forced reduction in inter-die bandwidth (which degrades product performance), or a die size increase to add pad rows, which cascades into yield and cost models that were already closed.

What Good Co-Design Looks Like

Teams that handle this well start with a pad budget, not a logic budget. Before any serious RTL partitioning begins, the package engineer and the system architect agree on a hard ceiling for signals crossing each die boundary. That ceiling comes from the pad ring geometry, the bump pitch, and the substrate routing budget simultaneously.

From that ceiling, the logic partition gets constructed to fit. Signals that would cross the boundary get either consolidated into wider interfaces (reducing pad count by increasing data width per pad) or pulled onto the same die entirely.

A few concrete practices matter here. First, run substrate escape routing simulations against multiple partition scenarios early, not just one. Second, treat bump count per boundary as a design constraint with the same weight as power or timing. Third, schedule a joint review between package and logic teams at the point where partition alternatives are still open, before any one option hardens.

None of this is exotic. It requires calendar coordination more than technical heroics.

The Deeper Issue

Pad-limited conditions are becoming the default, not the exception, as AI accelerators and HPC chiplets push logic density harder with each process node. The design flows most teams use were built when die area was the binding constraint. Those flows need updating.

When the pad ring fills before the silicon does, the packaging team stops being downstream. They become a co-equal input to partition planning from day one. The sooner that gets reflected in how programs are staffed and scheduled, the fewer late-stage surprises end up on the program manager's desk.