Why RDL Fanout Pitch Determines Chiplet Integration Density Before Anything Else

Before you argue about UCIe lane counts or bump pitch specifications, there is a more basic question that determines how many chiplets you can physically integrate in a given package area: how fine can your redistribution layer (RDL) fanout pitch actually get?

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RDL is the set of metal routing layers built directly on top of a wafer or panel, used in fan-out packaging to redistribute I/O from tight die pads out to coarser package-level connections. In a chiplet context, it does something even more demanding. It routes signals laterally between dies that were never designed to sit next to each other, bridging mismatched pad grids and connecting chiplets from different foundries, different nodes, and different pad pitches into a coherent system.

The pitch of those RDL lines and spaces sets a hard ceiling on routing density. A 2 µm line/space RDL can support roughly four times the routing tracks of an 8 µm line/space RDL in the same width. That difference cascades directly into how many signal connections you can make between two adjacent chiplets, which determines whether a given disaggregation makes electrical sense at all.

Consider what happens when you split a monolithic SoC into a compute chiplet and an I/O chiplet. You might need hundreds of high-speed interfaces crossing that die boundary every clock cycle. If your RDL pitch cannot support the required trace density, you either spread the chiplets farther apart (increasing package area and wire length), reduce interface width (hurting bandwidth), or add routing layers (raising cost and process complexity). None of those options are free.

High-density fan-out processes from TSMC (InFO_oS), Samsung (FOPLP variants), and ASE (FOCoS) have pushed RDL line/space down to 2 µm and below in production. TSMC's InFO with chip-on-wafer-on-substrate can achieve sub-2 µm RDL by leveraging wafer-level lithography rather than panel-level, where registration tolerances are tighter. That lithographic precision translates directly to routing headroom.

Here is a simplified view of how RDL pitch affects signal routing between two chiplets:

graph LR
    A[Chiplet A Pads] --> B(RDL Layer 1: fine pitch)
    B --> C(RDL Layer 2: redistribution)
    C --> D[Chiplet B Pads]
    B --> E{Pitch too coarse?}
    E --> F[/Reduce interface width or increase layers/]

Panel-level fan-out is where pitch limitations bite hardest. Panels are cheaper per unit area than wafers, but their larger format makes sub-5 µm lithography difficult to sustain across the full panel without yield-killing registration errors. For chiplet designs that need dense inter-die routing, panel-level processes often cannot deliver the pitch required, forcing the design back to wafer-level processes at higher cost. This is one reason high-performance computing chiplet packages still largely live on wafer-level substrates despite the cost pressure to move to panels.

Layer count matters too, but not in isolation. Adding RDL layers helps when you are routing-limited in the horizontal dimension; more layers give you more tracks. The problem is that each additional RDL layer adds process steps, increases package height, and introduces more opportunities for via misalignment. A design that requires six RDL layers to compensate for coarse pitch would often be better served by a finer-pitch process using three layers. The via stack between chiplets accumulates resistance and inductance with every added layer, which the signal integrity budget has to absorb.

Power delivery is also affected by RDL pitch, though it gets less attention than signaling. Fine-pitch RDL lines are narrower and carry less current before electromigration limits kick in. Designers routing power planes through RDL have to widen those traces, which consumes routing channels that signal lines would otherwise use. Balancing power and signal routing in RDL is an optimization problem that cannot be separated from the pitch capability of the process.

OSAT providers and IDMs making packaging decisions early in a chiplet program should treat RDL pitch as a first-order design input. Selecting a packaging process before understanding the inter-die routing density requirement is working the problem backwards. The required number of die-to-die connections, divided by the available routing width along each die edge, tells you the minimum RDL track density you need. From there, you can map to a process that actually supports it.

Bump pitch gets discussed constantly in chiplet integration conversations. RDL fanout pitch deserves equal time. It is the layer that translates your die-level electrical intent into something the package can physically realize, and when it is underspecified, no amount of clever interconnect protocol design rescues the integration.